A liquid crystal display panel by way of example, has pixel electrodes arrayed in the form of a matrix formed over the entire display surface area, the pixel electrodes being connected with the drain electrodes of respective thin-film transistors (as will be referred to as "TFT" hereinafter) formed adjacent to the pixel electrodes. The gate electrodes of the TFTs in each row of the matrix are connected to a corresponding gate bus while the source electrodes of the TFTs in each column are connected to a corresponding source bus. Upon a driving voltage being applied to a selected gate bus, the TFTs connected with the gate bus are turned on, so that the turned-on TFTs are supplied with respective image signals through the source buses whereby the corresponding pixel electrodes are loaded with electric charges according to the image signals.
FIG. 1 shows one example of the structure of each TFT such as a top gate TFT in such a matrix. As illustrated in FIG. 1, an insulation film 2 is formed on and all over one side surface of a glass substrate 1. Formed on the insulation film 2 are a source lead 3 and a drain lead 4 having at ends source electrode 3a and drain electrode 4a in opposed parallel relation. A semiconductor layer 5 of amorphous silicon (a-Si) overlies the insulation film 2 so as to extend between and overlap the opposed marginal edges of the source electrode 3a and the drain electrode 4a. The semiconductor layer 5 is covered by a gate insulation film 5 on which a gate electrode 7 is formed in confronting relation with the semiconductor layer 9.
With the TFT as shown in FIG. 1 it is preferred that the gate electrode 7 be formed such that the opposed side edges of the gate electrode 7 and the end edges of the source and drain electrodes 3a and 4a are in registration with each other because the ON-resistance of the TFT is increased if there is any portion of the semiconductor layer 5 in the channel region 50 between the source and drain electrodes 3a and 4a to which no gate voltage is applied. It is seen in the example of FIG. 1 that the formation is such that the opposed side edges of the gate electrode 7 will overlap the marginal edges of the source and drain electrodes 3a and 4a over the distance d. While this reduces the ON-resistance of the TFT, the response characteristics of the TFT are deteriorated due to parasitic capacitances produced between the gate electrode 7 and the source electrode 3a and between the gate electrode 7 and the drain electrode 4a.
One approach to overcoming these problems has been proposed by Sakoda, Matsumura et al as disclosed in the "IN-SITU CRYSTALLIZATION AND DOPING OF a-Si FILM BY MEANS OF SPIN-ON-GLASS" Mat. Res. Soc. Symp. Proc. Vol. 336. 1994. This approach will be described with reference to FIG. 2. A SOG (spin-on-glass) coating 9 doped with P atoms is applied as an insulation film onto a glass substrate and baked at 450.degree. C., followed by forming on the coating 9 an a-Si semiconductor layer 5 which is in turn covered with a gate insulation film 6. Then, a gate electrode 7 is formed on the gate insulation film 6 prior to forming source and drain leads 3 and 4, respectively. An excimer laser beam 8 is radiated as indicated by arrows 8 with the gate electrode 7 as a mask to melt those hatched portions of the semiconductor layer 5 which are not shaded by the gate electrode 7 to thereby cause P atoms to diffuse from the SOG into the melted portions of the semiconductor layer 5. Upon termination of the laser radiation, the melted portions of the semiconductor layer are allowed to cool down to form an n- poly-Si having a high electrical conductivity.
Next, contact holes 6H are formed through the gate insulation film 6 on the opposite sides of the gate electrode 7 to reach the opposite marginal sides of the semiconductor layer 5, and then source and drain leads 3 and 4 are formed on the gate insulation film 6 such that one end of each of the source and drain leads 3 and 4 fills the corresponding contact hole 6H so as to contact the semiconductor layer 5. It is thus possible to reduce the parasitic capacitances and ON-resistances since the hatched n.sup.+ poly-Si portions of the semiconductor layer serve as source and drain regions although the channel portion 5c of the layer remains a-Si.
However, there are difficulties in forming the SOG film uniformly and defectlessly over the entire large display surface area, because the SOG film 9 is inferior in film thickness distribution due to its being applied to the glass substrate by spin-coating and because the film is susceptible to cracks as it is subjected to baking especially when it is relatively thick. Such cracks can lead to pixel defects, breakage of source and gate buses, TFT defects, etc. Moreover, the baking of SOG at an elevated temperature of 400.degree. C. or higher is likely to cause distortion and/or shrinkage of the glass substrate.